GUC finalizes HBM4E IP design for TSMC’s N2P processMachine translation
GUC announced that its HBM4E PHY and controller IP for TSMC’s N2P process has been finalized and adopted for a customer AI ASIC. The IP supports 16Gbps data transfer and CoWoS-S/R/L packaging. A face-up version for 3D SoIC integrates TSVs for vertical signal and power transmission.
GUC finalizes HBM4E IP design for TSMC’s N2P process
GUC announced that its HBM4E PHY and controller IP for TSMC’s N2P process has been finalized and adopted for a customer AI ASIC. The IP supports 16Gbps data transfer and CoWoS-S/R/L packaging. A face-up version for 3D SoIC integrates TSVs for vertical signal and power transmission.
材料 bad68764b841401d88a1dd90694d4d8f；建议 647913860f0440e896370ad4fa624398；系统证据核验通过，非人工审稿。
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